The present invention relates generally to static random access memory (SRAM) cell, and, more particularly, to dual port SRAM cells.
Semiconductor memory devices include, for example, static random access memory, or SRAM, and dynamic random access memory, or DRAM. DRAM memory cell has only one transistor and one capacitor, so it provides a high degree of integration. But DRAM requires constant refreshing, its power consumption and slow speed limit its use mainly for computer main memories. The SRAM cell, on the other hand, is bi-stable, meaning it can maintain its state indefinitely as long as an adequate power is supplied. SRAM can operate at a higher speed and lower power dissipation, so computer cache memories use exclusively SRAMs. Other applications include embedded memories and networking equipment memories.
One well-known conventional structure of a SRAM cell is a six transistor (6T) cell that comprises six metal-oxide-semiconductor (MOS) transistors. Briefly, a 6T SRAM cell 100, as shown in FIG. 1, comprises two identical cross-coupled inverters 102 and 104 that form a latch circuit, i.e., one inverter's output connected to the other inverter's input. The latch circuit is connected between power and ground. Each inverter 102 or 104 comprises a NMOS pull-down transistor 115 or 125 and a PMOS pull-up transistor 110 or 120. The inverter's outputs serve as two storage nodes C and D, when one is pulled to low voltage, the other is pulled to high voltage. A complementary bit-line pair 150 and 155 is coupled to the pair of storage nodes C and D via a pair of pass-gate transistors 130 and 135, respectively. The gates of the pass-gate transistors 130 and 135 are commonly connected to a word-line 140. When the word-line voltage is switched to a system high voltage, or Vcc, the pass-gate transistors 130 and 135 are turned on to allow the storage nodes C and D to be accessible by the bit-line pair 150 and 155, respectively. When the word-line voltage is switched to a system low voltage, or Vss, the pass-gate transistors 130 and 135 are turned off and the storage nodes C and D are essentially isolated from the bit lines, although some leakage can occur. Nevertheless, as long as Vcc is maintained above a threshold, the state of the storage nodes C and D is maintained indefinitely.
Asynchronous multiprocessor systems require a means to transmit data between two independently running processors. Dual port memory provides a common memory accessible to both processors that can be used to share and transmit data and system status between the two processors. FIG. 2 shows a conventional eight-transistor (8-T) dual port SRAM cell 200. Essentially, it is a read port 202 added to the 6-T SRAM cell 100. The read port 202 comprises a read-port word-line 260, a read-port pass-gate NMOS transistor 270, a read-port pull-down NMOS transistor 275 and a read-port bit-line 280.
Referring to FIG. 2, the 6-T SRAM cell 100 can still perform read and write operations. The separate read port 202 can also perform read operation independent of the 6-T SRAM cell 100. So this cell can read data from cell 100 (pre-charging both bit-lines 250 and 255 to Vdd, and raising the voltage of gates 230 and 235 to high, then a sense-amplifier circuit detects a voltage difference between the bit-line pair 250 and 255), or from read port 202 (pre-charging a read-port bit-line 280 and raising the voltage of gate 260, then a sensing circuit detects the voltage at the read-port bit-line 280), or both cells 100 (to first circuit) and read port 202 (to second circuit). But during the data write cycle, only cell 100 is accessible.
Like the single-port 6-T SRAM cell, the conventional 8-T dual-port SRAM cell has a write disturb problem for the cells on the same word-line, which turns on all the pass-gate transistors thus exposes the storage nodes. Besides, the conventional 8-T dual-port SRAM cell has a large cell size due to eight transistors in total, and an additional read-port word-line and bit-line.
As such, what is desired is a SRAM cell that has the dual-port functionality while maintaining a relatively small cell size.